1. Field of the Invention
This invention relates generally to data transfers over a SCSI bus, and in particular to automated synchronous data transfers over a SCSI bus.
2. Description of Related Art
Prior single chip parallel SCSI host adapters have included a plurality of modules and an on-chip processor that controlled operation of the modules. For example, see U.S. Pat. No. 5,659,690, entitled xe2x80x9cProgrammably Configurable Host Adapter Integrated Circuit Including a RISC Processor,xe2x80x9d issued on Aug. 19, 1997 to Stuber et al., which is incorporated herein by reference.
A typical parallel SCSI host adapter 100 included a SCSI module 130 (FIG. 1), a sequencer 120, data FIFO memory circuit 160, a memory 140, and a host interface module 110 that were interconnected by an internal chip I/O bus CIOBUS, which was used for control of host adapter integrated circuit 100 both by a host microprocessor 170 through a host adapter driver 165 and by sequencer 120. The combination of host adapter driver 165, sequencer 120, and SCSI module 130 were used for controlling both synchronous and asynchronous transfers over SCSI bus 150
As is known to those of skill in the art, information transfers over SCSI bus 150 use a handshake method that utilizes request signals REQs and acknowledge signals ACKs. SCSI command, message, and status phases utilize only the asynchronous transfer mode in which an acknowledge signal ACK cannot be asserted until after a request signal REQ is asserted; request signal REQ cannot be de-asserted until acknowledge signal ACK is asserted; and acknowledge signal ACK cannot be de-asserted until signal REQ is re-asserted.
Synchronous data transfers are faster than asynchronous data transfers because the overhead is reduced. The SCSI data phase is the only phase that can transfer data using either a synchronous data transfer mode or an asynchronous data transfer mode. The synchronous data transfer mode is optional for the data phase, and must be negotiated between an initiator, e.g., host adapter 100, and a target device, e.g., any one of SCSI peripherals 151 and 152.
In the negotiation between initiator 100 and the target device, two parameters are determined, a transfer period and a REQ/ACK offset. The transfer period is the minimum time period from a rising edge of one request signal to the rising edge of the next request signal, and also is the minimum time period from a rising edge of one acknowledge signal to the rising edge of the next acknowledge signal. The width of the transfer period dictates the speed at which data can be transferred over SCSI bus 150. The REQ/ACK offset is a maximum number of request signals REQs that a target device can send over SCSI bus 150 before an acknowledge signal ACK is received from host adapter.
Since the transfer period and REQ/ACK offset are dependent upon characteristics of the target device, they can be different for each target device 151, 152 on SCSI bus 150. While FIG. 1 illustrates only two target devices, typically SCSI bus 150 can have up to sixteen target devices.
When host adapter 100 selects a target device, or is reselected by a target device, SCSI module 130 must be configured with the transfer period and the REQ/ACK offset for that target device. Typically, host adapter driver 165 provides the transfer period and the REQ/ACK offset in a sequencer control block (SCB) for the target device. Sequencer 120 transfers the transfer period and the REQ/ACK offset from the SCB for the selected or reselecting target device to a SCSI rate register and a SCSI offset register, respectively, in SCSI module 130 to configure SCSI module 130 for the data transfer.
This explanation of configuring SCSI module 130 assumed that host adapter driver had the REQ/ACK offset and the transfer period for the target device stored in a table in the host computer memory. However, initially the values of these parameters for a particular target device an unknown and must be determined by negotiation. The negotiation is done during the execution of a SCSI command specified in the SCB.
Host adapter driver 165 that manages host adapter 100 notifies sequencer 120 that a negotiation is required by loading an invalid transfer period in the SCB that is sent to host adapter 100. During execution of the SCB, sequencer 120 detects the invalid transfer period. Those of skill in the art will appreciate that sequencer 120 is a processor that executes instructions. Thus, when it is stated that sequencer 120 takes a particular action this means that an instruction or sequence of instructions executed by sequencer 120 configures sequencer 120 so that the action is performed.
Upon detection of the invalid transfer period, sequencer 120 causes SCSI module 130 to assert the SCSI attention signal at the appropriate time during execution of the SCSI command according to the SCSI protocol, i.e., sequencer 120 programs the hardware so that the SCSI attention signal can be generated. The target device can respond to the SCSI attention signal either by entering a Message Out phase, or by ignoring the SCSI attention signal and entering a Command phase. If the SCSI attention signal is ignored, sequencer 120 continues with execution of the SCB by configuring SCSI module 130 for an asynchronous data transfer.
However, if the target device responds by entering the Message Out phase, sequencer 120 interrupts host adapter driver 165 with a request to execute the negotiation. Execution of the SCB by sequencer 120 is stopped for the negotiation because neither the transfer period nor the REQ/ACK offset is available to sequencer 120.
In response to the interrupt, host adapter driver 165 conducts the negotiation to determine the values for the two parameters. When the negotiation is completed, host adapter driver 165 saves the values for the two parameters in a table within the host computer memory for future use. Host adapter driver 165 also loads the values in the SCB currently being executed by sequencer 120, and into the appropriate registers in SCSI module 130. Finally, host adapter driver 165 releases sequencer 120 so that execution of the SCB can continue. Hence, all the operations associated with configuring SCSI module 120 for a synchronous transfer are performed by sequencer 120 and host adapter driver 165. The simple transfer of the transfer period and the REQ/ACK offset from the SCB to the appropriate registers required several sequencer instructions.
According to the principles of this invention, automating the setup of the data transfers enhances a data transfer during a SCSI data phase. Unlike the prior art host adapters that required a plurality of sequencer operations to configure the prior art SCSI module with the synchronous data transfer parameters, a SCSI module of this invention automatically configures the synchronous data transfer parameters using only hardware within the SCSI module of a parallel SCSI host adapter integrated circuit. The automatic configuration of the synchronous data transfer parameters eliminates the sequence of sequencer firmware instructions that were previously required to perform these operations as well as the time required to execute those firmware instructions.
In one embodiment, a parallel SCSI host adapter integrated circuit includes a memory containing a table having a plurality of entries. Each entry in the plurality of entries is a parameter used to configure the parallel SCSI host adapter integrated circuit for a data transfer over a SCSI bus to a target device. A target identification register stores a pointer to the table. A SCSI transfer parameter register is coupled to the memory. An entry in the plurality of entries pointed to by the value stored in the target identification register is loaded automatically into the SCSI transfer parameter register when a target identification (ID) is loaded into the target identification register.
Another SCSI transfer parameter register also is coupled to the memory so that another entry in the plurality of entries pointed to by the value stored in the target identification register is loaded automatically into the another SCSI transfer parameter register when the target ID is loaded into the target identification register.
A decoder circuit connected to the SCSI transfer parameter register has a set SCSI attention signal output line, an enable SCSI asynchronous transfer output line, and a reset SCSI attention signal output line. When a value in the SCSI transfer register indicates an asynchronous data transfer, the decoder circuit generates an active signal on the enable SCSI asynchronous transfer output line.
When a value in the SCSI transfer register indicates an asynchronous data transfer, and a value in the another SCSI transfer register indicates that a synchronous negotiation is needed, the decoder generates an active signal on the set SCSI attention signal output line. If the target device generates an active request signal followed by a command phase on the SCSI bus, the decoder drops the active signal on the set SCSI attention signal output line, and generates active signals on the reset SCSI attention signal output line and the enable SCSI asynchronous transfer output line.
The SCSI module of this invention includes a table that includes an entry for each target device on the SCSI bus. The entry specifies the mode of data transfer over the SCSI bus, either an asynchronous transfer or a synchronous transfer. If a synchronous transfer is specified, the table automatically provides a synchronous REQ/ACK offset and a synchronous transfer period from an on-chip table upon a target identification register being loaded with a target ID. If the entry indicates an asynchronous data transfer and another entry indicates that a synchronous negotiation is needed, the decoder automatically asserts a set SCSI attention signal.
All of these operations are performed automatically without the use of any processor, e.g., either the on-chip sequencer or the host computer processor. Consequently, both processors can perform other operations at the same time that the SCSI module of this invention automatically configures the parameters for the data transfer. In addition, the sequence of instructions that the on-chip sequencer used in the prior art to configure the parameters for the data transfer can be eliminated. Both of those factors improve the performance of the parallel SCSI host adapter integrated circuit that includes this invention relative to the prior art parallel SCSI host adapter integrated circuit.